Conductive polymer/si interfaces at back side of solar cells
The present invention relates to a solar cell (1) comprising a substrate (2) of p-type silicon or n-type silicon, wherein the substrate (2) comprises - a front side (2a) the surface of which is at least partially covered with at least one passivation layer (3) and - a back side (2b), wherein the bac...
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creator | ZIELKE DIMITRI SCHMIDT JAN LEVENICH WILFRIED SCHEEL ARNULF HERTEIS MATTHIAS ELSCHNER ANDREAS |
description | The present invention relates to a solar cell (1) comprising a substrate (2) of p-type silicon or n-type silicon, wherein the substrate (2) comprises - a front side (2a) the surface of which is at least partially covered with at least one passivation layer (3) and - a back side (2b), wherein the back side (2b) of the substrate (2) is at least partially covered with a conductive polymer layer (4) and wherein at least one of the following conditions a) and b) is fulfilled: a) the conductive polymer layer (4) is at least partially in direct contact with the surface of the p-type or n-type silicon; b) the conductive polymer layer (4) comprises a cationic conductive polymer and a polymeric anion in a weight ratio cationic conductive polymer : polymeric anion of greater than 0.4. The present invention also relates to a process for the preparation of a solar cell, to a solar cell obtainable by this process and to a solar module.
本发明涉及太阳能电池(1),其包含p-型硅或n-型硅的基底(2),其中基底(2)包含:-正面(2a),其表面至少部分地被至少个钝化层(3)覆盖,和-背面(2b),其中基底(2) |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN107431129A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN107431129A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN107431129A3</originalsourceid><addsrcrecordid>eNrjZLBxzs9LKU0uySxLVSjIz6nMTS3SL85UyMwrSS1KS0xOLVZILFFISkzOVijOTElVyE9TKM7PSSxSSE7NySnmYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQVA_XmpJfHOfoYG5ibGhoZGlo7GxKgBANHQL3o</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Conductive polymer/si interfaces at back side of solar cells</title><source>esp@cenet</source><creator>ZIELKE DIMITRI ; SCHMIDT JAN ; LEVENICH WILFRIED ; SCHEEL ARNULF ; HERTEIS MATTHIAS ; ELSCHNER ANDREAS</creator><creatorcontrib>ZIELKE DIMITRI ; SCHMIDT JAN ; LEVENICH WILFRIED ; SCHEEL ARNULF ; HERTEIS MATTHIAS ; ELSCHNER ANDREAS</creatorcontrib><description>The present invention relates to a solar cell (1) comprising a substrate (2) of p-type silicon or n-type silicon, wherein the substrate (2) comprises - a front side (2a) the surface of which is at least partially covered with at least one passivation layer (3) and - a back side (2b), wherein the back side (2b) of the substrate (2) is at least partially covered with a conductive polymer layer (4) and wherein at least one of the following conditions a) and b) is fulfilled: a) the conductive polymer layer (4) is at least partially in direct contact with the surface of the p-type or n-type silicon; b) the conductive polymer layer (4) comprises a cationic conductive polymer and a polymeric anion in a weight ratio cationic conductive polymer : polymeric anion of greater than 0.4. The present invention also relates to a process for the preparation of a solar cell, to a solar cell obtainable by this process and to a solar module.
本发明涉及太阳能电池(1),其包含p-型硅或n-型硅的基底(2),其中基底(2)包含:-正面(2a),其表面至少部分地被至少个钝化层(3)覆盖,和-背面(2b),其中基底(2)</description><language>chi ; eng</language><subject>ELECTRICITY</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171201&DB=EPODOC&CC=CN&NR=107431129A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20171201&DB=EPODOC&CC=CN&NR=107431129A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZIELKE DIMITRI</creatorcontrib><creatorcontrib>SCHMIDT JAN</creatorcontrib><creatorcontrib>LEVENICH WILFRIED</creatorcontrib><creatorcontrib>SCHEEL ARNULF</creatorcontrib><creatorcontrib>HERTEIS MATTHIAS</creatorcontrib><creatorcontrib>ELSCHNER ANDREAS</creatorcontrib><title>Conductive polymer/si interfaces at back side of solar cells</title><description>The present invention relates to a solar cell (1) comprising a substrate (2) of p-type silicon or n-type silicon, wherein the substrate (2) comprises - a front side (2a) the surface of which is at least partially covered with at least one passivation layer (3) and - a back side (2b), wherein the back side (2b) of the substrate (2) is at least partially covered with a conductive polymer layer (4) and wherein at least one of the following conditions a) and b) is fulfilled: a) the conductive polymer layer (4) is at least partially in direct contact with the surface of the p-type or n-type silicon; b) the conductive polymer layer (4) comprises a cationic conductive polymer and a polymeric anion in a weight ratio cationic conductive polymer : polymeric anion of greater than 0.4. The present invention also relates to a process for the preparation of a solar cell, to a solar cell obtainable by this process and to a solar module.
本发明涉及太阳能电池(1),其包含p-型硅或n-型硅的基底(2),其中基底(2)包含:-正面(2a),其表面至少部分地被至少个钝化层(3)覆盖,和-背面(2b),其中基底(2)</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBxzs9LKU0uySxLVSjIz6nMTS3SL85UyMwrSS1KS0xOLVZILFFISkzOVijOTElVyE9TKM7PSSxSSE7NySnmYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQVA_XmpJfHOfoYG5ibGhoZGlo7GxKgBANHQL3o</recordid><startdate>20171201</startdate><enddate>20171201</enddate><creator>ZIELKE DIMITRI</creator><creator>SCHMIDT JAN</creator><creator>LEVENICH WILFRIED</creator><creator>SCHEEL ARNULF</creator><creator>HERTEIS MATTHIAS</creator><creator>ELSCHNER ANDREAS</creator><scope>EVB</scope></search><sort><creationdate>20171201</creationdate><title>Conductive polymer/si interfaces at back side of solar cells</title><author>ZIELKE DIMITRI ; SCHMIDT JAN ; LEVENICH WILFRIED ; SCHEEL ARNULF ; HERTEIS MATTHIAS ; ELSCHNER ANDREAS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN107431129A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2017</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>ZIELKE DIMITRI</creatorcontrib><creatorcontrib>SCHMIDT JAN</creatorcontrib><creatorcontrib>LEVENICH WILFRIED</creatorcontrib><creatorcontrib>SCHEEL ARNULF</creatorcontrib><creatorcontrib>HERTEIS MATTHIAS</creatorcontrib><creatorcontrib>ELSCHNER ANDREAS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZIELKE DIMITRI</au><au>SCHMIDT JAN</au><au>LEVENICH WILFRIED</au><au>SCHEEL ARNULF</au><au>HERTEIS MATTHIAS</au><au>ELSCHNER ANDREAS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Conductive polymer/si interfaces at back side of solar cells</title><date>2017-12-01</date><risdate>2017</risdate><abstract>The present invention relates to a solar cell (1) comprising a substrate (2) of p-type silicon or n-type silicon, wherein the substrate (2) comprises - a front side (2a) the surface of which is at least partially covered with at least one passivation layer (3) and - a back side (2b), wherein the back side (2b) of the substrate (2) is at least partially covered with a conductive polymer layer (4) and wherein at least one of the following conditions a) and b) is fulfilled: a) the conductive polymer layer (4) is at least partially in direct contact with the surface of the p-type or n-type silicon; b) the conductive polymer layer (4) comprises a cationic conductive polymer and a polymeric anion in a weight ratio cationic conductive polymer : polymeric anion of greater than 0.4. The present invention also relates to a process for the preparation of a solar cell, to a solar cell obtainable by this process and to a solar module.
本发明涉及太阳能电池(1),其包含p-型硅或n-型硅的基底(2),其中基底(2)包含:-正面(2a),其表面至少部分地被至少个钝化层(3)覆盖,和-背面(2b),其中基底(2)</abstract><oa>free_for_read</oa></addata></record> |
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title | Conductive polymer/si interfaces at back side of solar cells |
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