SCHEDULER DEVICE AND METHOD FOR DYNAMIC LOOP-TO-PROCESSOR MAPPING
A scheduler device and a method for mapping program blocks to cores of a heterogeneous multi-core system, comprising at least two types of cores, c1, c2, the method comprising the steps of: estimating (S1), in run-time, available resources of the heterogeneous multi-core system for parallel executio...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | A scheduler device and a method for mapping program blocks to cores of a heterogeneous multi-core system, comprising at least two types of cores, c1, c2, the method comprising the steps of: estimating (S1), in run-time, available resources of the heterogeneous multi-core system for parallel execution of at least one program block; determining (S2) a first number of loops, n1, and a second number of loops, n2, of the program block, to be associated with each of the at least two types of cores of the heterogeneous multi-core system, wherein a total number of loops, N=n1+n2, of the program block is to be executed in the heterogeneous multi-core system on the estimated available resources; checking (S3) a power consumption condition, and if the power consumption condition is not satisfied, modifying a clock frequency, f1 of the first type, c1 cores and determining again the first, n1, and the second, n2, number of loops to be associated with each of the at least two types, c1, c2, of cores; and parallel executing |
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