Data interval selection and continuous output implementing method based on FPGA

The present invention provides a data interval selection and continuous output implementing method based on the FPGA. The method comprises the following steps: S1, using a fifo memory to cache data in the FPGA; and S2, defining an interface for the FPGA interface module to be connected with the fifo...

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Bibliographische Detailangaben
Hauptverfasser: FAN YUJIN, ZHANG JIANJUN, TIAN LI, ZHANG CHUNTAN
Format: Patent
Sprache:chi ; eng
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Zusammenfassung:The present invention provides a data interval selection and continuous output implementing method based on the FPGA. The method comprises the following steps: S1, using a fifo memory to cache data in the FPGA; and S2, defining an interface for the FPGA interface module to be connected with the fifo memory, cooperating a corresponding control signal, implementing selection of required data for transmission, and implementing continuous address output. The data interval selection and continuous output implementing method based on the FPGA provided by the present invention is relatively easy to implement, only requiring the control signal can implement prioritized transmission of important data, the data is transmitted and is ensured to be continuously output according to the requirement, and the fifo is used to ensure data not to be lost during the data transmission process. 本发明提供了种基于FPGA实现数据间隔选择连续输出的方法,包括以下步骤:S1、在FPGA中使用fifo存储器缓存数据;S2、对FPGA接口模块连接fifo存储器的接口进行定义,配合相应的控制信号,实现选择需要的数据传输,并实现连续地址输出。本发明所述的基于FPGA实现数据间隔