MICROPROCESSOR 2X CORE DESIGN
A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals to clock the operations within the microprocessor and bus clock signals to clock data transfer op...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A microprocessor that operates at the speed of the bus or at a speed which is a multiple of the bus speed on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals to clock the operations within the microprocessor and bus clock signals to clock data transfer operations between the microprocessor and the bus. |
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