Placing and routing method for implementing back bias in FDSOI

The present disclosure provides a placing and routing method for implementing back bias in fully depleted silicon-on-insulator. In accordance with some illustrative embodiments herein, the placing and routing method comprises placing a first plurality of a standard tap well cell along a first direction, the standard tap well cell being formed by: routing a p-BIAS wire VPW and an n-BIAS wire VNW in a first a first metallization layer, and routing a power rail and a ground rail in a second metallization layer, the VPW and the VNW extending across each of the power and ground rail, wherein the VPWs of the first plurality of standard tap well cells are continuously connected and the VNWs of the first plurality of standard tap well cells are continuously connected. 本发明提供了种用以在完全耗尽绝缘体上硅(FDSOI)中实施后偏置(back bias)的布局及布线方法。依据本文中的些示例实施例，该布局及布线方法包括沿第方向布局第多个标准连接阱单元，该标准连接阱单元通过以下方式形成：在第第金属化层中布线p-BIAS线VPW及n-BIAS线VNW，以及在第二金属化层中布线功率轨线及接地轨线，该VPW及该VNW延伸跨越各该功率轨线及接地轨线，其中，该第多个标准连接阱单元的该VPW连续连接且该第多个标准连接阱单元的该VNW连续连接。