Dynamic selection of output delay in a memory control device

In an example, a memory control device (104) includes an output circuit (310), an output delay unit (312), and a write-levelization controller (302). The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system (106) having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write- levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions. 在个示例中，存储器控制装置(104)包括输出电路(310)、输出延迟单元(312)和写入均衡控制器(302)。所述输出电路被耦接以向具有多个列的同步动态随机存取存储器(SDRAM)系统(106)提供包括数据信号或数据选通信号的输出信号。所述输出延迟