DATA PROCESSOR

A processor is disclosed. The processor includes a first-receiver-node for receiving a first-receiver-signal, a second-receiver-node for receiving a second-receiver-signal, a first-output-node for coupling to a digital-baseband-processor, a second-output-node for coupling to the digital-baseband-processor and a first-active-data-pipe extending between the first-receiver-node and the first-output-node. The first-active-data-pipe includes a first-analogue-to-digital-converter comprising a first-ADC-input coupled to the first-receiver-node and a first-ADC-output coupled to the first-output-node. The first-analogue-to-digital-converter is configured to provide a first-digital-signal to the first-output-node. The processor comprises a first-reference-node and a configurable-data-pipe extending between the second-receiver-node and the second-output-node. 本公开提出种处理器，所述处理器包括：用于接收第接收器信号的第接收器节点；用于接收第二接收器信号的第二接收器节点；用于耦合到数字基带处理器的第输出节点；用于耦合到所述数字基带处理器的第二输出节点；在所述第接收器节点和所述第输出节点之间延伸的第现用数据管道。