SEAL-RING STRUCTURE FOR STACKING INTEGRATED CIRCUITS

A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer. 本发明实施例提供三维集成电路芯片。在些实施例中，第集成电路芯片包含第半导体基板、第内连线结构位于第半导体基板上、以及第混合接合结构位于第内连线结构上。第混合接合结构包含混