System and method to speed up PLL lock time on subsequent calibrations via stored band values

The invention discloses a system and method to speed up PLL lock time on subsequent calibrations via stored band values. A method and apparatus and computer program product for calibrating a Phase Lock Loop (PLL) that reduces a PLL lock time for subsequent calibrations to thereby improve an overall system time and latency. The system and method for calibrating obviates effects of Process, Voltage and Temperature to achieve a faster PLL lock. 本发明揭示种经由已储存波段值在后续校准时加速PLL锁定时间的系统及方法，其中，用于校准锁相回路(PLL)的方法与设备及计算机程序产品缩短用于后续校准的PLL锁定时间，从而改善整体系统时间及延迟。此用于校准的系统及方法排除制程、电压及温度的影响，以更快达成PLL锁定。