Self-latch sense timing sequence in a one-time-programmable memory architecture

The invention relates to self-latch sense timing sequence in a one-time-programmable memory architecture. A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs. 本发明涉及种单次可编程存储器架构中的自锁存感测时序。可编程存储器(19)包含自锁存读取数据路径。感测放大器(28)感测位线处的电压电平，所述位线传送在其相关联的列中的所选择的存储器单元(32)的数据状态。耦合到所述感测放大器(28)的输出的数据锁存器(30)传递所述感测到的数据状态。提供在所述读取数据路径中接收所述数据