Silicon-on-insulator (SOI) low-resistance lateral high-voltage device and manufacturing method thereof

The invention provides a silicon-on-insulator (SOI) low-resistance lateral high-voltage device and a manufacturing method thereof. The manufacturing method comprises the following steps of taking an SOI as a substrate, forming an N-type linear variable doping thick SOI layer and a thin silicon layer...

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Hauptverfasser: ZHANG BO, ZHANG WENTONG, DING BAILANG, QIAO MING, ZENG LIYAO, CAO HOUHUA, ZHAN ZHENYA, XIAO QIANQIAN
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creator ZHANG BO
ZHANG WENTONG
DING BAILANG
QIAO MING
ZENG LIYAO
CAO HOUHUA
ZHAN ZHENYA
XIAO QIANQIAN
description The invention provides a silicon-on-insulator (SOI) low-resistance lateral high-voltage device and a manufacturing method thereof. The manufacturing method comprises the following steps of taking an SOI as a substrate, forming an N-type linear variable doping thick SOI layer and a thin silicon layer drift region, forming a thin silicon layer region, namely a thick dielectric layer, and forming a Pwell region; and forming an Nwell region, forming a gate oxide layer, forming a poly-silicon gate electrode, forming an N strips, forming a P strip, performing injection of a first P-type heavy-doping region, a first N-type heavy-doping region and a second N-type heavy-doping region to form ohmic contact, etching a first-layer contact hole of a leading-out electrode, depositing aluminum metal, and forming a source contact electrode and a drain contact electrode. The manufacturing method is highly compatible with a traditional process and has universality; with the manufactured device, the device area can be effective
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN106952809A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN106952809A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN106952809A3</originalsourceid><addsrcrecordid>eNqNirEKwjAQQLs4iPoP56ZDoCqKHaUouuhQ93KklyaQ5kpyrb9vBz9AePCG9-aZqZx3moOacCENHoUjbKrXYwuePypSckkwaIIpUUQP1rVWjewFW4KGRjc1DA10GAaDWoboQgsdieUGxFIkNstsZtAnWv28yNa367u8K-q5ptSjpkBSl89dfiqO-3NeXA7_PF9Fvz97</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Silicon-on-insulator (SOI) low-resistance lateral high-voltage device and manufacturing method thereof</title><source>esp@cenet</source><creator>ZHANG BO ; ZHANG WENTONG ; DING BAILANG ; QIAO MING ; ZENG LIYAO ; CAO HOUHUA ; ZHAN ZHENYA ; XIAO QIANQIAN</creator><creatorcontrib>ZHANG BO ; ZHANG WENTONG ; DING BAILANG ; QIAO MING ; ZENG LIYAO ; CAO HOUHUA ; ZHAN ZHENYA ; XIAO QIANQIAN</creatorcontrib><description>The invention provides a silicon-on-insulator (SOI) low-resistance lateral high-voltage device and a manufacturing method thereof. The manufacturing method comprises the following steps of taking an SOI as a substrate, forming an N-type linear variable doping thick SOI layer and a thin silicon layer drift region, forming a thin silicon layer region, namely a thick dielectric layer, and forming a Pwell region; and forming an Nwell region, forming a gate oxide layer, forming a poly-silicon gate electrode, forming an N strips, forming a P strip, performing injection of a first P-type heavy-doping region, a first N-type heavy-doping region and a second N-type heavy-doping region to form ohmic contact, etching a first-layer contact hole of a leading-out electrode, depositing aluminum metal, and forming a source contact electrode and a drain contact electrode. The manufacturing method is highly compatible with a traditional process and has universality; with the manufactured device, the device area can be effective</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170714&amp;DB=EPODOC&amp;CC=CN&amp;NR=106952809A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170714&amp;DB=EPODOC&amp;CC=CN&amp;NR=106952809A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ZHANG BO</creatorcontrib><creatorcontrib>ZHANG WENTONG</creatorcontrib><creatorcontrib>DING BAILANG</creatorcontrib><creatorcontrib>QIAO MING</creatorcontrib><creatorcontrib>ZENG LIYAO</creatorcontrib><creatorcontrib>CAO HOUHUA</creatorcontrib><creatorcontrib>ZHAN ZHENYA</creatorcontrib><creatorcontrib>XIAO QIANQIAN</creatorcontrib><title>Silicon-on-insulator (SOI) low-resistance lateral high-voltage device and manufacturing method thereof</title><description>The invention provides a silicon-on-insulator (SOI) low-resistance lateral high-voltage device and a manufacturing method thereof. The manufacturing method comprises the following steps of taking an SOI as a substrate, forming an N-type linear variable doping thick SOI layer and a thin silicon layer drift region, forming a thin silicon layer region, namely a thick dielectric layer, and forming a Pwell region; and forming an Nwell region, forming a gate oxide layer, forming a poly-silicon gate electrode, forming an N strips, forming a P strip, performing injection of a first P-type heavy-doping region, a first N-type heavy-doping region and a second N-type heavy-doping region to form ohmic contact, etching a first-layer contact hole of a leading-out electrode, depositing aluminum metal, and forming a source contact electrode and a drain contact electrode. The manufacturing method is highly compatible with a traditional process and has universality; with the manufactured device, the device area can be effective</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNirEKwjAQQLs4iPoP56ZDoCqKHaUouuhQ93KklyaQ5kpyrb9vBz9AePCG9-aZqZx3moOacCENHoUjbKrXYwuePypSckkwaIIpUUQP1rVWjewFW4KGRjc1DA10GAaDWoboQgsdieUGxFIkNstsZtAnWv28yNa367u8K-q5ptSjpkBSl89dfiqO-3NeXA7_PF9Fvz97</recordid><startdate>20170714</startdate><enddate>20170714</enddate><creator>ZHANG BO</creator><creator>ZHANG WENTONG</creator><creator>DING BAILANG</creator><creator>QIAO MING</creator><creator>ZENG LIYAO</creator><creator>CAO HOUHUA</creator><creator>ZHAN ZHENYA</creator><creator>XIAO QIANQIAN</creator><scope>EVB</scope></search><sort><creationdate>20170714</creationdate><title>Silicon-on-insulator (SOI) low-resistance lateral high-voltage device and manufacturing method thereof</title><author>ZHANG BO ; ZHANG WENTONG ; DING BAILANG ; QIAO MING ; ZENG LIYAO ; CAO HOUHUA ; ZHAN ZHENYA ; XIAO QIANQIAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN106952809A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ZHANG BO</creatorcontrib><creatorcontrib>ZHANG WENTONG</creatorcontrib><creatorcontrib>DING BAILANG</creatorcontrib><creatorcontrib>QIAO MING</creatorcontrib><creatorcontrib>ZENG LIYAO</creatorcontrib><creatorcontrib>CAO HOUHUA</creatorcontrib><creatorcontrib>ZHAN ZHENYA</creatorcontrib><creatorcontrib>XIAO QIANQIAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ZHANG BO</au><au>ZHANG WENTONG</au><au>DING BAILANG</au><au>QIAO MING</au><au>ZENG LIYAO</au><au>CAO HOUHUA</au><au>ZHAN ZHENYA</au><au>XIAO QIANQIAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Silicon-on-insulator (SOI) low-resistance lateral high-voltage device and manufacturing method thereof</title><date>2017-07-14</date><risdate>2017</risdate><abstract>The invention provides a silicon-on-insulator (SOI) low-resistance lateral high-voltage device and a manufacturing method thereof. The manufacturing method comprises the following steps of taking an SOI as a substrate, forming an N-type linear variable doping thick SOI layer and a thin silicon layer drift region, forming a thin silicon layer region, namely a thick dielectric layer, and forming a Pwell region; and forming an Nwell region, forming a gate oxide layer, forming a poly-silicon gate electrode, forming an N strips, forming a P strip, performing injection of a first P-type heavy-doping region, a first N-type heavy-doping region and a second N-type heavy-doping region to form ohmic contact, etching a first-layer contact hole of a leading-out electrode, depositing aluminum metal, and forming a source contact electrode and a drain contact electrode. The manufacturing method is highly compatible with a traditional process and has universality; with the manufactured device, the device area can be effective</abstract><oa>free_for_read</oa></addata></record>
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ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Silicon-on-insulator (SOI) low-resistance lateral high-voltage device and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T17%3A20%3A34IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=ZHANG%20BO&rft.date=2017-07-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN106952809A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true