Silicon-on-insulator (SOI) low-resistance lateral high-voltage device and manufacturing method thereof

The invention provides a silicon-on-insulator (SOI) low-resistance lateral high-voltage device and a manufacturing method thereof. The manufacturing method comprises the following steps of taking an SOI as a substrate, forming an N-type linear variable doping thick SOI layer and a thin silicon layer...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: ZHANG BO, ZHANG WENTONG, DING BAILANG, QIAO MING, ZENG LIYAO, CAO HOUHUA, ZHAN ZHENYA, XIAO QIANQIAN
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The invention provides a silicon-on-insulator (SOI) low-resistance lateral high-voltage device and a manufacturing method thereof. The manufacturing method comprises the following steps of taking an SOI as a substrate, forming an N-type linear variable doping thick SOI layer and a thin silicon layer drift region, forming a thin silicon layer region, namely a thick dielectric layer, and forming a Pwell region; and forming an Nwell region, forming a gate oxide layer, forming a poly-silicon gate electrode, forming an N strips, forming a P strip, performing injection of a first P-type heavy-doping region, a first N-type heavy-doping region and a second N-type heavy-doping region to form ohmic contact, etching a first-layer contact hole of a leading-out electrode, depositing aluminum metal, and forming a source contact electrode and a drain contact electrode. The manufacturing method is highly compatible with a traditional process and has universality; with the manufactured device, the device area can be effective