Wafer Level Chip Scale Package Interconnects and Methods of Manufacture Thereof

A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to late...

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Bibliographische Detailangaben
Hauptverfasser:	CHUNG-SHI LIU, CHIH-WEI LIN, CHENG-TAR WU, MING-DA CHENG, CHUNNG LIN, HUI-MIN HUANG
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	A method of forming a wafer level chip scale package interconnect may include: forming a post-passivation interconnect (PPI) layer over a substrate; forming an interconnect over the PPI layer; and releasing a molding compound material over the substrate, the molding compound material flowing to laterally encapsulate a portion of the interconnect. 种形成晶圆级芯片尺寸包装互连件的方法包括：在衬底上形成后钝化互连(PPI)层；在PPI层上形成互连件；并且在衬底上释放模塑料，流动模塑料以横向密封部分互连件。本发明实施例涉及晶圆级芯片尺寸封装互连件及其制造方法。