D flip-flop hold time measuring circuit and measuring method

The invention provides a D flip-flop hold time measuring circuit and measuring method. The D flip-flop hold time measuring circuit comprises an input unit, a converting unit and an output unit. The D flip-flop hold time measuring circuit also comprises a variable voltage source, which is used for applying a variable voltage to the input unit. By adjusting the variable voltage, time delay of a single buffer and a single phase inverter is changed. The hold time of a D flip-flop is no longer associated with the time delay of the buffer itself, but is associated with time delay difference of the buffer caused by voltage adjustable minimum step length. The invention also provides a single buffer and single phase inverter average time-delay measuring circuit and method. The measuring circuit comprises a buffer delay chain, a phase inverter delay chain and a variable voltage generation circuit. The variable voltage generation circuit applies a variable voltage to the buffer delay chain and the phase inverter delay c