Burst mode read controllable SRAM

The application discloses a burst mode read controllable static random access memory (SRAM). A static random access memory (SRAM) 104 includes an array 202 of storage cells arranged as rows and columns and a read controller 204 to manage reading from the storage cells. The array 202 of storage cells includes word lines that correspond to the rows and bit lines that correspond to the columns. The read controller 204 is configured to receive a precharge signal 222 and a word line signal 224 and identify consecutive reads from storage cells accessed via a same one of the word lines. The read controller 204 is further configured to, based on the precharge signal 222 and the word line pulse signal 224 indicating that the SRAM 104 is to operate in a partial burst mode, precharge the bit lines no more than once during the consecutive reads and charge the same one of the word lines after each read of the consecutive reads. 本申请公开了突发模式读可控SRAM。静态随机存取存储器(SRAM)104包含布置为行和列的存储单元的阵列202，以及用于管理所述存储单元的读取的读控制器204。所述存储单元的阵列202包含对