Encoder signal filtering method and filtering system based on FPGA

The invention discloses an encoder signal filtering method and a filtering system based on FPGA. The encoder signal filtering method based on FPGA comprises the following steps: S1, the encoder outputs 1Vpp signals; S2, the 1Vpp signals are amplified and processed; S3, analog-to-digital conversion is carried out on the amplified 1Vpp signals; S4, filtering processing is carried out on the 1Vpp signals after analog-to-digital conversion; and S5, a phase value is queried and stored. The 1Vpp signals outputted by an incremental encoder are subjected to filtering processing, the signal accuracy is improved, algorithm compensation is carried out on the 1Vpp signals conveniently, and the phase calculation is more accurate. 本发明公开了种基于FPGA的编码器信号的滤波方法及滤波系统，基于FPGA的编码器信号的滤波方法包括以下步骤：S、编码器输出1Vpp信号；S、对所述1Vpp信号进行放大处理；S、对放大后的1Vpp信号进行模数转换；S、对模数转换后的1Vpp信号进行滤波处理；S、查询出相位值并进行存储。本发明会对增量式编码器输出的1Vpp信号进行滤波处理，从而提高了信号准确度，方便对1Vpp信号进行算法补偿，使得相位计算更加准确。