Timing controller and display device comprising same

The invention provides a timing controller and a display device comprising the same. The timing controller comprises a memory controller, a decompressor, a row buffer area and an image signal processing part, wherein the memory controller is used for reading compressed LUT (Look Up Table) data from an external memory; the decompressor is used for decompressing the compressed LUT data received from the memory controller and generating original LUT data before compression; the row buffer area is used for temporarily storing the original LUT data received from the decompressor; and the image signal processing part is used for using the original LUT data stored in the row buffer area to compensate an MURA defect of inputted image signal data. 本发明提供种时序控制器及包含该时序控制器的显示装置。所述时序控制器包含：从外部存储器读取压缩LUT数据的存储器控制器；对从所述存储器控制器接收的所述压缩LUT数据进行解压缩，并产生压缩前的原始LUT数据的解压缩器；临时存储从所述解压缩器接收的所述原始LUT数据的行缓冲区；利用在所述行缓冲区中存储的所述原始LUT数据，来补偿输入的图像信号数据的MURA缺陷(MURA defect)的图像信号处理部。