D-type flip-flop and signal transmission method thereof
The present invention discloses a D-type flip-flop and a signal transmission method thereof. The D-type flip-flop comprises a time-delay inversion unit In, a first phase inverter I4, a first PMOS transistor M1, a second PMOS transistor M2, a first NMOS transistor M3, a second NMOS transistor M4, a t...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The present invention discloses a D-type flip-flop and a signal transmission method thereof. The D-type flip-flop comprises a time-delay inversion unit In, a first phase inverter I4, a first PMOS transistor M1, a second PMOS transistor M2, a first NMOS transistor M3, a second NMOS transistor M4, a third NMOS transistor M5 and a fourth NMOS transistor M6; the time-delay inversion unit In is used for outputting delayed reverse clock signals; the input end of the first inverter I4 is connected with the input end of data signals; the drain of the first NMOS transistor M3 and the drain of the first PMOS transistor M1 are connected at a first node; the drain of the second NMOS transistor M4 and the drain of the second PMOS transistor M2 are connected at a second node; the gate of the second NMOS transistor M4 is connected with the gate of the first NMOS transistor M3 and receives the clock signals; the source of the third NMOS transistor M5 is connected with the input end of the first phase inverter I4; and the gat |
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