Packaging substrate and manufacturing method therefor

The invention discloses a packaging substrate and a manufacturing method therefor. An embodiment provides the packaging substrate, wherein packaging substrate comprises a supporting carrying board and a thin type substrate; the supporting carrying board comprises a carrier and a metal dielectric lay...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: DARCY HU, BARRY LI, KK KUO, TIM ZUO, POTATO SHI, MASON LIN, KENNY LO, JERRY CAO, KHMER ZHAO, EVA LIU
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator DARCY HU
BARRY LI
KK KUO
TIM ZUO
POTATO SHI
MASON LIN
KENNY LO
JERRY CAO
KHMER ZHAO
EVA LIU
description The invention discloses a packaging substrate and a manufacturing method therefor. An embodiment provides the packaging substrate, wherein packaging substrate comprises a supporting carrying board and a thin type substrate; the supporting carrying board comprises a carrier and a metal dielectric layer with a first surface and a second surface which are arranged oppositely; the first surface is in contact with the carrier; the thin type substrate comprises a first circuit layer, a first dielectric layer which is laminated on the first circuit layer and is in contact with the second surface of the metal dielectric layer, a second circuit layer which is formed in the other side, relative to the first circuit layer, of the first dielectric layer, and a first conductive through hole which is embedded in the first dielectric layer and equipped with opposite first end and second end; the first end is electrically connected with the first circuit layer while the second end is electrically connected with the second ci
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN106229309A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN106229309A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN106229309A3</originalsourceid><addsrcrecordid>eNrjZDANSEzOTkzPzEtXKC5NKi4pSixJVUjMS1HITcwrTUtMLiktAsnlppZk5KcolGSkFqWm5RfxMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JJ4Zz9DAzMjI0tjA0tHY2LUAACbIC2l</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Packaging substrate and manufacturing method therefor</title><source>esp@cenet</source><creator>DARCY HU ; BARRY LI ; KK KUO ; TIM ZUO ; POTATO SHI ; MASON LIN ; KENNY LO ; JERRY CAO ; KHMER ZHAO ; EVA LIU</creator><creatorcontrib>DARCY HU ; BARRY LI ; KK KUO ; TIM ZUO ; POTATO SHI ; MASON LIN ; KENNY LO ; JERRY CAO ; KHMER ZHAO ; EVA LIU</creatorcontrib><description>The invention discloses a packaging substrate and a manufacturing method therefor. An embodiment provides the packaging substrate, wherein packaging substrate comprises a supporting carrying board and a thin type substrate; the supporting carrying board comprises a carrier and a metal dielectric layer with a first surface and a second surface which are arranged oppositely; the first surface is in contact with the carrier; the thin type substrate comprises a first circuit layer, a first dielectric layer which is laminated on the first circuit layer and is in contact with the second surface of the metal dielectric layer, a second circuit layer which is formed in the other side, relative to the first circuit layer, of the first dielectric layer, and a first conductive through hole which is embedded in the first dielectric layer and equipped with opposite first end and second end; the first end is electrically connected with the first circuit layer while the second end is electrically connected with the second ci</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20161214&amp;DB=EPODOC&amp;CC=CN&amp;NR=106229309A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20161214&amp;DB=EPODOC&amp;CC=CN&amp;NR=106229309A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DARCY HU</creatorcontrib><creatorcontrib>BARRY LI</creatorcontrib><creatorcontrib>KK KUO</creatorcontrib><creatorcontrib>TIM ZUO</creatorcontrib><creatorcontrib>POTATO SHI</creatorcontrib><creatorcontrib>MASON LIN</creatorcontrib><creatorcontrib>KENNY LO</creatorcontrib><creatorcontrib>JERRY CAO</creatorcontrib><creatorcontrib>KHMER ZHAO</creatorcontrib><creatorcontrib>EVA LIU</creatorcontrib><title>Packaging substrate and manufacturing method therefor</title><description>The invention discloses a packaging substrate and a manufacturing method therefor. An embodiment provides the packaging substrate, wherein packaging substrate comprises a supporting carrying board and a thin type substrate; the supporting carrying board comprises a carrier and a metal dielectric layer with a first surface and a second surface which are arranged oppositely; the first surface is in contact with the carrier; the thin type substrate comprises a first circuit layer, a first dielectric layer which is laminated on the first circuit layer and is in contact with the second surface of the metal dielectric layer, a second circuit layer which is formed in the other side, relative to the first circuit layer, of the first dielectric layer, and a first conductive through hole which is embedded in the first dielectric layer and equipped with opposite first end and second end; the first end is electrically connected with the first circuit layer while the second end is electrically connected with the second ci</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDANSEzOTkzPzEtXKC5NKi4pSixJVUjMS1HITcwrTUtMLiktAsnlppZk5KcolGSkFqWm5RfxMLCmJeYUp_JCaW4GRTfXEGcP3dSC_PjU4oLE5NS81JJ4Zz9DAzMjI0tjA0tHY2LUAACbIC2l</recordid><startdate>20161214</startdate><enddate>20161214</enddate><creator>DARCY HU</creator><creator>BARRY LI</creator><creator>KK KUO</creator><creator>TIM ZUO</creator><creator>POTATO SHI</creator><creator>MASON LIN</creator><creator>KENNY LO</creator><creator>JERRY CAO</creator><creator>KHMER ZHAO</creator><creator>EVA LIU</creator><scope>EVB</scope></search><sort><creationdate>20161214</creationdate><title>Packaging substrate and manufacturing method therefor</title><author>DARCY HU ; BARRY LI ; KK KUO ; TIM ZUO ; POTATO SHI ; MASON LIN ; KENNY LO ; JERRY CAO ; KHMER ZHAO ; EVA LIU</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN106229309A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>DARCY HU</creatorcontrib><creatorcontrib>BARRY LI</creatorcontrib><creatorcontrib>KK KUO</creatorcontrib><creatorcontrib>TIM ZUO</creatorcontrib><creatorcontrib>POTATO SHI</creatorcontrib><creatorcontrib>MASON LIN</creatorcontrib><creatorcontrib>KENNY LO</creatorcontrib><creatorcontrib>JERRY CAO</creatorcontrib><creatorcontrib>KHMER ZHAO</creatorcontrib><creatorcontrib>EVA LIU</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DARCY HU</au><au>BARRY LI</au><au>KK KUO</au><au>TIM ZUO</au><au>POTATO SHI</au><au>MASON LIN</au><au>KENNY LO</au><au>JERRY CAO</au><au>KHMER ZHAO</au><au>EVA LIU</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Packaging substrate and manufacturing method therefor</title><date>2016-12-14</date><risdate>2016</risdate><abstract>The invention discloses a packaging substrate and a manufacturing method therefor. An embodiment provides the packaging substrate, wherein packaging substrate comprises a supporting carrying board and a thin type substrate; the supporting carrying board comprises a carrier and a metal dielectric layer with a first surface and a second surface which are arranged oppositely; the first surface is in contact with the carrier; the thin type substrate comprises a first circuit layer, a first dielectric layer which is laminated on the first circuit layer and is in contact with the second surface of the metal dielectric layer, a second circuit layer which is formed in the other side, relative to the first circuit layer, of the first dielectric layer, and a first conductive through hole which is embedded in the first dielectric layer and equipped with opposite first end and second end; the first end is electrically connected with the first circuit layer while the second end is electrically connected with the second ci</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language chi ; eng
recordid cdi_epo_espacenet_CN106229309A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Packaging substrate and manufacturing method therefor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T18%3A02%3A46IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DARCY%20HU&rft.date=2016-12-14&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN106229309A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true