Memory devices including blocking layers

The invention provides a memory device including a cell region and a peripheral circuit region adjacent the cell region. A plurality of gate electrode layers and insulating layers are stacked on the substrate in the cell region, and a plurality of circuit devices are in the peripheral circuit region. A first interlayer insulating layer is on the substrate in the peripheral circuit region and covers the plurality of circuit devices, and a second interlayer insulating layer is on the substrate in the cell region and the peripheral circuit region. A blocking layer is on the plurality of circuit devices between the first and second interlayer insulating layers. The blocking layer is on an upper surface, of the first interlayer insulating layer, and a side surface of the blocking layer is covered by the second interlayer insulating layer. 本发明提供种存储器件，该存储器件包括单元区域和邻近单元区域的外围电路区域。多个栅电极层和绝缘层层叠在衬底上于单元区域中，并且多个电路器件在外围电路区域中。第层间绝缘层在衬底上于外围电路区域中并且覆盖所述多个电路器件，第二层间绝缘层在衬底上于单元区域和外围电路区域中。阻挡层在所述多个电路器件上于第和第二层间绝缘层之间。阻挡层在第层间绝缘层的上表面上，阻挡层