Current regulation for accurate and low-cost voltage measurements at the wafer level

A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold. 本发明提供了种用于半导体器件大电流参数精确测试的测试系统和测试技术。运行时，所述测试系统向所述半导体器件提供电流并测量所述器件的电压。所述测试系统可用测得的电压计算所述大电流半导体器件的接通电阻。在项技术中，多个与焊盘接触的施力针的排布为同样与所述焊盘接触的个或多个感应针形成等电阻通道。在另项技术中，通过调节流经所述施力针的电流