Testing system for aiming at 80C186 architecture interface board
The invention relates to a testing system for aiming at an 80C186 architecture interface board. The testing system comprises an FPGA least system circuit, a communication interface circuit, an Arinc429 signal transmitting circuit and a sequential logic control circuit. The FPGA least system is mainl...
Gespeichert in:
| Hauptverfasser: | , , , , , |
|---|---|
| Format: | Patent |
| Sprache: | chi ; eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | WU TENG ZHAO GUIFANG LUO YUNHU TANG QIYUAN LIANG XIAOFEN ZHOU YONGJUN |
| description | The invention relates to a testing system for aiming at an 80C186 architecture interface board. The testing system comprises an FPGA least system circuit, a communication interface circuit, an Arinc429 signal transmitting circuit and a sequential logic control circuit. The FPGA least system is mainly composed of seven small parts, namely a clock input circuit, a resetting input circuit, a JTAG interface circuit, a program configuring circuit, a voltage supply circuit, a phase-locked loop circuit and an indicating lamp circuit. In the communication interface circuit, because a hardware language in which a serial-port communication protocol can be built is utilized on the FPGA, a corresponding adapter interface chip is utilized for RS232, RS422 and RS485 interface communication in the communication interface circuit. The testing system can supply a testing facility and a testing method for interface board testing of the 80C186 processor architecture board, thereby realizing quick product fault positioning, shor |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN106094795A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN106094795A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN106094795A3</originalsourceid><addsrcrecordid>eNrjZHAISS0uycxLVyiuLC5JzVVIyy9SSMzMBYkklihYGDgbWpgpJBYlZ2SWpCaXlBalKmTmlaQWpSUmpyok5ScWpfAwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTiAqDCvNSSeGc_QwMzA0sTc0tTR2Ni1AAAT7IwUw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Testing system for aiming at 80C186 architecture interface board</title><source>esp@cenet</source><creator>WU TENG ; ZHAO GUIFANG ; LUO YUNHU ; TANG QIYUAN ; LIANG XIAOFEN ; ZHOU YONGJUN</creator><creatorcontrib>WU TENG ; ZHAO GUIFANG ; LUO YUNHU ; TANG QIYUAN ; LIANG XIAOFEN ; ZHOU YONGJUN</creatorcontrib><description>The invention relates to a testing system for aiming at an 80C186 architecture interface board. The testing system comprises an FPGA least system circuit, a communication interface circuit, an Arinc429 signal transmitting circuit and a sequential logic control circuit. The FPGA least system is mainly composed of seven small parts, namely a clock input circuit, a resetting input circuit, a JTAG interface circuit, a program configuring circuit, a voltage supply circuit, a phase-locked loop circuit and an indicating lamp circuit. In the communication interface circuit, because a hardware language in which a serial-port communication protocol can be built is utilized on the FPGA, a corresponding adapter interface chip is utilized for RS232, RS422 and RS485 interface communication in the communication interface circuit. The testing system can supply a testing facility and a testing method for interface board testing of the 80C186 processor architecture board, thereby realizing quick product fault positioning, shor</description><language>chi ; eng</language><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL ; CONTROLLING ; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS ; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS ; PHYSICS ; REGULATING</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161109&DB=EPODOC&CC=CN&NR=106094795A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20161109&DB=EPODOC&CC=CN&NR=106094795A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WU TENG</creatorcontrib><creatorcontrib>ZHAO GUIFANG</creatorcontrib><creatorcontrib>LUO YUNHU</creatorcontrib><creatorcontrib>TANG QIYUAN</creatorcontrib><creatorcontrib>LIANG XIAOFEN</creatorcontrib><creatorcontrib>ZHOU YONGJUN</creatorcontrib><title>Testing system for aiming at 80C186 architecture interface board</title><description>The invention relates to a testing system for aiming at an 80C186 architecture interface board. The testing system comprises an FPGA least system circuit, a communication interface circuit, an Arinc429 signal transmitting circuit and a sequential logic control circuit. The FPGA least system is mainly composed of seven small parts, namely a clock input circuit, a resetting input circuit, a JTAG interface circuit, a program configuring circuit, a voltage supply circuit, a phase-locked loop circuit and an indicating lamp circuit. In the communication interface circuit, because a hardware language in which a serial-port communication protocol can be built is utilized on the FPGA, a corresponding adapter interface chip is utilized for RS232, RS422 and RS485 interface communication in the communication interface circuit. The testing system can supply a testing facility and a testing method for interface board testing of the 80C186 processor architecture board, thereby realizing quick product fault positioning, shor</description><subject>CONTROL OR REGULATING SYSTEMS IN GENERAL</subject><subject>CONTROLLING</subject><subject>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</subject><subject>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</subject><subject>PHYSICS</subject><subject>REGULATING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAISS0uycxLVyiuLC5JzVVIyy9SSMzMBYkklihYGDgbWpgpJBYlZ2SWpCaXlBalKmTmlaQWpSUmpyok5ScWpfAwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTiAqDCvNSSeGc_QwMzA0sTc0tTR2Ni1AAAT7IwUw</recordid><startdate>20161109</startdate><enddate>20161109</enddate><creator>WU TENG</creator><creator>ZHAO GUIFANG</creator><creator>LUO YUNHU</creator><creator>TANG QIYUAN</creator><creator>LIANG XIAOFEN</creator><creator>ZHOU YONGJUN</creator><scope>EVB</scope></search><sort><creationdate>20161109</creationdate><title>Testing system for aiming at 80C186 architecture interface board</title><author>WU TENG ; ZHAO GUIFANG ; LUO YUNHU ; TANG QIYUAN ; LIANG XIAOFEN ; ZHOU YONGJUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN106094795A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2016</creationdate><topic>CONTROL OR REGULATING SYSTEMS IN GENERAL</topic><topic>CONTROLLING</topic><topic>FUNCTIONAL ELEMENTS OF SUCH SYSTEMS</topic><topic>MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS</topic><topic>PHYSICS</topic><topic>REGULATING</topic><toplevel>online_resources</toplevel><creatorcontrib>WU TENG</creatorcontrib><creatorcontrib>ZHAO GUIFANG</creatorcontrib><creatorcontrib>LUO YUNHU</creatorcontrib><creatorcontrib>TANG QIYUAN</creatorcontrib><creatorcontrib>LIANG XIAOFEN</creatorcontrib><creatorcontrib>ZHOU YONGJUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WU TENG</au><au>ZHAO GUIFANG</au><au>LUO YUNHU</au><au>TANG QIYUAN</au><au>LIANG XIAOFEN</au><au>ZHOU YONGJUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Testing system for aiming at 80C186 architecture interface board</title><date>2016-11-09</date><risdate>2016</risdate><abstract>The invention relates to a testing system for aiming at an 80C186 architecture interface board. The testing system comprises an FPGA least system circuit, a communication interface circuit, an Arinc429 signal transmitting circuit and a sequential logic control circuit. The FPGA least system is mainly composed of seven small parts, namely a clock input circuit, a resetting input circuit, a JTAG interface circuit, a program configuring circuit, a voltage supply circuit, a phase-locked loop circuit and an indicating lamp circuit. In the communication interface circuit, because a hardware language in which a serial-port communication protocol can be built is utilized on the FPGA, a corresponding adapter interface chip is utilized for RS232, RS422 and RS485 interface communication in the communication interface circuit. The testing system can supply a testing facility and a testing method for interface board testing of the 80C186 processor architecture board, thereby realizing quick product fault positioning, shor</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | chi ; eng |
| recordid | cdi_epo_espacenet_CN106094795A |
| source | esp@cenet |
| subjects | CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING |
| title | Testing system for aiming at 80C186 architecture interface board |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T14%3A28%3A34IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WU%20TENG&rft.date=2016-11-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN106094795A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |