Syncronization of interrupt processing to reduce power consumption

A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time,unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time,the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed. 公开了种处理器，并且该处理器包括：至少个核心，包括第核心；以及中断延迟逻辑。中断延迟逻辑用于在第时间接收第中断以及延迟处理第中断达开始于第时间的第时间延迟，除非在第核心处理第二中断的第二时间处第中断挂起。如果在第二时间处第中断挂起，则中断延迟逻辑指示第核心在第时间延迟完成之前开始处理第中断。其他实施例被公开并要求保护。