Dynamic storage based on open bit line structure

Dynamic storage based on open bit line structure

The invention relates to a dynamic storage based on an open bit line structure. The dynamic storage comprises a decoder circuit, a sense amplifier and a plurality of dual-storage units, wherein the decoder circuit comprises a first decoding unit and a second decoding unit which have the same structu...

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Hauptverfasser: Tan Jie, Alexander, Yu Bing, Duan Huifu
Format: Patent
Sprache:chi ; eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator Tan Jie
Alexander
Yu Bing
Duan Huifu
description The invention relates to a dynamic storage based on an open bit line structure. The dynamic storage comprises a decoder circuit, a sense amplifier and a plurality of dual-storage units, wherein the decoder circuit comprises a first decoding unit and a second decoding unit which have the same structure, an input end of a first XOR gate circuit is connected with an external address signal RA , the other input end of the first XOR gate circuit is connected with a cfg_dualcell signal, and an output end of a first phase inverter controls a bit line Wl of one dual-storage unit in a storage unit array module to be opened; and an input end of a second XOR gate circuit is connected with an inverted signal/RAI of the external address signal RA , the other input end of the second XOR gate circuit is connected with the cfg_dualcell signal, and an output end of a second phase inverter controls the other bit line Wl of one dual-storage unit in the storage unit array module to be opened. According to the dynamic storage, th
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN105895147A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN105895147A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN105895147A3</originalsourceid><addsrcrecordid>eNrjZDBwqcxLzM1MViguyS9KTE9VSEosTk1RyM9TyC9IzVNIyixRyMnMSwVKF5Uml5QWpfIwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknhnP0MDUwtLU0MTc0djYtQAAEeFKyc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Dynamic storage based on open bit line structure</title><source>esp@cenet</source><creator>Tan Jie ; Alexander ; Yu Bing ; Duan Huifu</creator><creatorcontrib>Tan Jie ; Alexander ; Yu Bing ; Duan Huifu</creatorcontrib><description>The invention relates to a dynamic storage based on an open bit line structure. The dynamic storage comprises a decoder circuit, a sense amplifier and a plurality of dual-storage units, wherein the decoder circuit comprises a first decoding unit and a second decoding unit which have the same structure, an input end of a first XOR gate circuit is connected with an external address signal RA , the other input end of the first XOR gate circuit is connected with a cfg_dualcell signal, and an output end of a first phase inverter controls a bit line Wl of one dual-storage unit in a storage unit array module to be opened; and an input end of a second XOR gate circuit is connected with an inverted signal/RAI of the external address signal RA , the other input end of the second XOR gate circuit is connected with the cfg_dualcell signal, and an output end of a second phase inverter controls the other bit line Wl of one dual-storage unit in the storage unit array module to be opened. According to the dynamic storage, th</description><language>chi ; eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160824&amp;DB=EPODOC&amp;CC=CN&amp;NR=105895147A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160824&amp;DB=EPODOC&amp;CC=CN&amp;NR=105895147A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tan Jie</creatorcontrib><creatorcontrib>Alexander</creatorcontrib><creatorcontrib>Yu Bing</creatorcontrib><creatorcontrib>Duan Huifu</creatorcontrib><title>Dynamic storage based on open bit line structure</title><description>The invention relates to a dynamic storage based on an open bit line structure. The dynamic storage comprises a decoder circuit, a sense amplifier and a plurality of dual-storage units, wherein the decoder circuit comprises a first decoding unit and a second decoding unit which have the same structure, an input end of a first XOR gate circuit is connected with an external address signal RA , the other input end of the first XOR gate circuit is connected with a cfg_dualcell signal, and an output end of a first phase inverter controls a bit line Wl of one dual-storage unit in a storage unit array module to be opened; and an input end of a second XOR gate circuit is connected with an inverted signal/RAI of the external address signal RA , the other input end of the second XOR gate circuit is connected with the cfg_dualcell signal, and an output end of a second phase inverter controls the other bit line Wl of one dual-storage unit in the storage unit array module to be opened. According to the dynamic storage, th</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBwqcxLzM1MViguyS9KTE9VSEosTk1RyM9TyC9IzVNIyixRyMnMSwVKF5Uml5QWpfIwsKYl5hSn8kJpbgZFN9cQZw_d1IL8-NTigsTk1LzUknhnP0MDUwtLU0MTc0djYtQAAEeFKyc</recordid><startdate>20160824</startdate><enddate>20160824</enddate><creator>Tan Jie</creator><creator>Alexander</creator><creator>Yu Bing</creator><creator>Duan Huifu</creator><scope>EVB</scope></search><sort><creationdate>20160824</creationdate><title>Dynamic storage based on open bit line structure</title><author>Tan Jie ; Alexander ; Yu Bing ; Duan Huifu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN105895147A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2016</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Tan Jie</creatorcontrib><creatorcontrib>Alexander</creatorcontrib><creatorcontrib>Yu Bing</creatorcontrib><creatorcontrib>Duan Huifu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tan Jie</au><au>Alexander</au><au>Yu Bing</au><au>Duan Huifu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Dynamic storage based on open bit line structure</title><date>2016-08-24</date><risdate>2016</risdate><abstract>The invention relates to a dynamic storage based on an open bit line structure. The dynamic storage comprises a decoder circuit, a sense amplifier and a plurality of dual-storage units, wherein the decoder circuit comprises a first decoding unit and a second decoding unit which have the same structure, an input end of a first XOR gate circuit is connected with an external address signal RA , the other input end of the first XOR gate circuit is connected with a cfg_dualcell signal, and an output end of a first phase inverter controls a bit line Wl of one dual-storage unit in a storage unit array module to be opened; and an input end of a second XOR gate circuit is connected with an inverted signal/RAI of the external address signal RA , the other input end of the second XOR gate circuit is connected with the cfg_dualcell signal, and an output end of a second phase inverter controls the other bit line Wl of one dual-storage unit in the storage unit array module to be opened. According to the dynamic storage, th</abstract><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title Dynamic storage based on open bit line structure
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-13T16%3A57%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tan%20Jie&rft.date=2016-08-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN105895147A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true