Interlayer dielectric layer forming method and semiconductor device forming method
The invention provides an interlayer dielectric layer forming method. After an interlayer dielectric layer is formed through chemical vapor deposition, the interlayer dielectric layer is annealed for the first time, and the interlayer dielectric layer is etched to form a contact hole. After the cont...
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Format: | Patent |
Sprache: | chi ; eng |
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Zusammenfassung: | The invention provides an interlayer dielectric layer forming method. After an interlayer dielectric layer is formed through chemical vapor deposition, the interlayer dielectric layer is annealed for the first time, and the interlayer dielectric layer is etched to form a contact hole. After the contact hole is formed, the interlayer dielectric layer is annealed for the second time by making use of the role of the contact hole in increasing the surface area of the interlayer dielectric layer. Thus, avoids in the interlayer dielectric layer are eliminated completely, and the quality of the interlayer dielectric layer is improved. When the thickness of an interlayer dielectric layer is large, an interlayer dielectric layer of better quality can be obtained through the method. The invention further provides a semiconductor device forming method. A device structure is formed in a substrate in advance. After the second annealing, a wiring structure is formed through the contact hole to electrically connect the devi |
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