Instruction and logic for memory access in a clustered wide-execution machine

A processor includes a Level-2 (L2) cache, a first and second cluster of execution units, and a first and second data cache unit (DCU) communicatively coupled to the respective clusters of execution units and to the L2 cache. The DCUs each include a data cache and logic to receive a memory operation from an execution unit, respond to the memory operation with information from the data cache when the information is available in the data cache, and retrieve the information from the L2 cache when the information is unavailable in the data cache. The processor further includes logic to maintain contents of the data cache of the first DCU as equal to contents of the data cache of the second DCU at all clock cycles of operation of the processor. 一种处理器包括2级（L2）高速缓存、第一和第二执行单元集群、以及通信地耦合到相应执行单元集群并且耦合到L2高速缓存的第一和第二数据高速缓存单元（DCU）。DCU均包括数据高速缓存以及用于下述的逻辑：从执行单元接收存储器操作、当信息在数据高速缓存中可用时，用来自数据高速缓存的信息对存储器操作进行响应，并且当信息在数据高速缓存中不可用时，从L2高速缓存取回信息。处理器进一步包括用于下述的逻辑：在处理器的操作的所有时钟周期，将第一DCU的数据高速缓存的内容维持为等于第二DCU的数据高速缓存的内容。