Method for verifying consistency between layout and schematic on basis of process design kit

The invention discloses a method for verifying the consistency between a layout and a schematic on the basis of a process design kit. According to the method, device serial numbers are automatically added to the port names of parameterized devices in a QA library through adopting an automatic process, so that the uniqueness of all the port names in the QA library is achieved so as to achieve the requirement of LVS QA, the generation time of an LVS QA library is decreased, more comprehensive LVS QA is obtained and the human cost is saved; and the method can be applied to all the technology nodes at present, and is wide in application. 本发明公开了一种基于工艺设计包的版图与原理图一致性验证方法，通过采用自动化流程使得QA库中的参数化器件的端口名称自动加上器件序列号，从而达到了所有端口名称在QA库中的惟一性，以达到LVS QA的要求，不仅减少了LVS QA库的产生时间，获得了更全面的LVS QA，且节约了人力成本，并能够适用于目前所有的技术节点，应用广泛。