MOSFET package structure and wafer-level fabrication method thereof

The invention discloses an MOSFET package structure and a wafer-level fabrication method thereof. The package structure comprises a chip, wherein the chip comprises a source, a grid, a drain region and a heavily doped region; the source and the grid are electrically connected to a first electric conductor and a second electric conductor on the upper surface of the chip respectively; at least one hole or slot, which extends to the heavily doped region is formed in the drain region; a metal layer is arranged on the inner wall of the hole or slot; and the metal layer is connected with a third electric conductor on the upper surface of the chip as a drain. The current of the heavily doped region on the lower surface of a vertical-structure MOSFET is led to the upper surface of the MOSFET; and the source, the grid and the drain are located at the same side surface, so that wafer-level package is facilitated; a good heat dissipation effect of the chip is ensured by the large-area metal layer in the slot; the metal