Dynamically-tuned-gyro digital rebalance loop based on FPGA (Field-Programmable Gate Array)

The invention belongs to the technical field of closed-loop control of a loop of a dynamically tuned gyro, and concretely relates to a dynamically-tuned-gyro digital rebalance loop based on FPGA (Field-Programmable Gate Array). The dynamically-tuned-gyro digital rebalance loop comprises a gyro body layer, a hardware circuit layer and a FPGA abstraction layer. A single FPGA chip is used for realizing ADC sampling control, DAC output control, control algorithm and the like of the digital rebalance loop, FPGA can be used for controlling, and also can realize complex control algorithm by inlaying a Nios II processor, so that the dimension of the rebalance loop is substantially reduced, and also a software is employed for finishing algorithm design of a trap filter, an integrator and correction algorithm and the like, and thus debugging is relatively flexible.