Improved XOR gate logic unit circuit

The invention discloses an improved XOR gate logic unit circuit. The improved XOR gate logic unit circuit includes a first stage circuit composed of PMOS transistors P1 and P2 as well as NMOS transistors N1 and N2, and a second stage circuit composed of PMOS transistors P3, P4 and P5 as well as NMOS transistors N3, N4 and N5. In the first stage circuit, the PMOS transistor P1 and the PMOS transistor P2 are connected in parallel, and the NMOS transistor N1 and the NMOS transistor N2 are connected in parallel. In the second stage circuit, the PMOS transistor P3 and the PMOS transistor P4 are connected in parallel and then are connected in series with the PMOS transistor P5, and the NMOS transistor N3 and the NMOS transistor N3 are connected in parallel, and then are connected in series with the NMOS transistor N5. According to the improved XOR gate logic unit circuit, 10 transistors are adopted, and compared with a conventional XOR gate logic unit circuit, two fewer transistors are adopted, and XOR operation lo