Semiconductor package and manufacturing method therefor

The invention provides a semiconductor package lowering internal stress generated between a support substrste and a bonding material and with high reliability. The semiconductor package is characterized in that the semiconductor package includes a support substrate; a stress relaxation layer provide...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HASHIMOTO, KIYOAKI, TAKEHARA, YASUYUKI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The invention provides a semiconductor package lowering internal stress generated between a support substrste and a bonding material and with high reliability. The semiconductor package is characterized in that the semiconductor package includes a support substrate; a stress relaxation layer provided on a main surface of the support substrate; a semiconductor device located on the stress relaxation layer; an encapsulation material covering the semiconductor device, the encapsulation material being formed of an insulating material different from that of the stress relaxation layer; a line running through the encapsulation material and electrically connected to the semiconductor device; and an external terminal electrically connected to the line. Where the support substrate has an elastic modulus of A, the stress relaxation layer has an elastic modulus of B, and the encapsulation material has an elastic modulus of C under a same temperature condition, the relationship of A>C>B or C>A>B is obtained.