Package substrate and manufacturing method thereof
The invention relates to a package substrate and a manufacturing method thereof. According to the embodiment of the invention, the package substrate comprises at least one capacitance element and a multi-layer line structure, wherein the package substrate further comprises a metal top layer, a metal...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | OU XIANXUN LUO GUANGLIN PENG YUJING |
| description | The invention relates to a package substrate and a manufacturing method thereof. According to the embodiment of the invention, the package substrate comprises at least one capacitance element and a multi-layer line structure, wherein the package substrate further comprises a metal top layer, a metal bottom layer and at least one metal inner layer; the at least one metal inner layer is arranged between the metal top layer and the metal bottom layer; a top-layer line structure in the multi-layer line structure is arranged on the metal top layer; a bottom-layer line structure in the multi-layer line structure is arranged on the metal bottom layer; a side capacitance electrode plate of the at least one capacitance element and at least one inner-layer line structure in the multi-layer line structure are arranged on the at least one metal inner layer; and the thickness of the at least one inner-layer line structure is less than those of the top-layer line structure and the bottom-layer line structure. According to the package substrate and the manufacturing method thereof provided by the embodiment of the invention, high-quality embedded capacitance elements can be obtained; and the thickness of the package substrate is effectively controlled. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN105244348A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN105244348A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN105244348A3</originalsourceid><addsrcrecordid>eNrjZDAKSEzOTkxPVSguTSouKUosSVVIzEtRyE3MK01LTC4pLcrMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfHOfoYGpkYmJsYmFo7GxKgBAOcVLFU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Package substrate and manufacturing method thereof</title><source>esp@cenet</source><creator>OU XIANXUN ; LUO GUANGLIN ; PENG YUJING</creator><creatorcontrib>OU XIANXUN ; LUO GUANGLIN ; PENG YUJING</creatorcontrib><description>The invention relates to a package substrate and a manufacturing method thereof. According to the embodiment of the invention, the package substrate comprises at least one capacitance element and a multi-layer line structure, wherein the package substrate further comprises a metal top layer, a metal bottom layer and at least one metal inner layer; the at least one metal inner layer is arranged between the metal top layer and the metal bottom layer; a top-layer line structure in the multi-layer line structure is arranged on the metal top layer; a bottom-layer line structure in the multi-layer line structure is arranged on the metal bottom layer; a side capacitance electrode plate of the at least one capacitance element and at least one inner-layer line structure in the multi-layer line structure are arranged on the at least one metal inner layer; and the thickness of the at least one inner-layer line structure is less than those of the top-layer line structure and the bottom-layer line structure. According to the package substrate and the manufacturing method thereof provided by the embodiment of the invention, high-quality embedded capacitance elements can be obtained; and the thickness of the package substrate is effectively controlled.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160113&DB=EPODOC&CC=CN&NR=105244348A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160113&DB=EPODOC&CC=CN&NR=105244348A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OU XIANXUN</creatorcontrib><creatorcontrib>LUO GUANGLIN</creatorcontrib><creatorcontrib>PENG YUJING</creatorcontrib><title>Package substrate and manufacturing method thereof</title><description>The invention relates to a package substrate and a manufacturing method thereof. According to the embodiment of the invention, the package substrate comprises at least one capacitance element and a multi-layer line structure, wherein the package substrate further comprises a metal top layer, a metal bottom layer and at least one metal inner layer; the at least one metal inner layer is arranged between the metal top layer and the metal bottom layer; a top-layer line structure in the multi-layer line structure is arranged on the metal top layer; a bottom-layer line structure in the multi-layer line structure is arranged on the metal bottom layer; a side capacitance electrode plate of the at least one capacitance element and at least one inner-layer line structure in the multi-layer line structure are arranged on the at least one metal inner layer; and the thickness of the at least one inner-layer line structure is less than those of the top-layer line structure and the bottom-layer line structure. According to the package substrate and the manufacturing method thereof provided by the embodiment of the invention, high-quality embedded capacitance elements can be obtained; and the thickness of the package substrate is effectively controlled.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAKSEzOTkxPVSguTSouKUosSVVIzEtRyE3MK01LTC4pLcrMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfHOfoYGpkYmJsYmFo7GxKgBAOcVLFU</recordid><startdate>20160113</startdate><enddate>20160113</enddate><creator>OU XIANXUN</creator><creator>LUO GUANGLIN</creator><creator>PENG YUJING</creator><scope>EVB</scope></search><sort><creationdate>20160113</creationdate><title>Package substrate and manufacturing method thereof</title><author>OU XIANXUN ; LUO GUANGLIN ; PENG YUJING</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN105244348A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>OU XIANXUN</creatorcontrib><creatorcontrib>LUO GUANGLIN</creatorcontrib><creatorcontrib>PENG YUJING</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OU XIANXUN</au><au>LUO GUANGLIN</au><au>PENG YUJING</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Package substrate and manufacturing method thereof</title><date>2016-01-13</date><risdate>2016</risdate><abstract>The invention relates to a package substrate and a manufacturing method thereof. According to the embodiment of the invention, the package substrate comprises at least one capacitance element and a multi-layer line structure, wherein the package substrate further comprises a metal top layer, a metal bottom layer and at least one metal inner layer; the at least one metal inner layer is arranged between the metal top layer and the metal bottom layer; a top-layer line structure in the multi-layer line structure is arranged on the metal top layer; a bottom-layer line structure in the multi-layer line structure is arranged on the metal bottom layer; a side capacitance electrode plate of the at least one capacitance element and at least one inner-layer line structure in the multi-layer line structure are arranged on the at least one metal inner layer; and the thickness of the at least one inner-layer line structure is less than those of the top-layer line structure and the bottom-layer line structure. According to the package substrate and the manufacturing method thereof provided by the embodiment of the invention, high-quality embedded capacitance elements can be obtained; and the thickness of the package substrate is effectively controlled.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_CN105244348A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Package substrate and manufacturing method thereof |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T02%3A32%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OU%20XIANXUN&rft.date=2016-01-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN105244348A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |