Inverted trapezoidal grid CMOS integrated device with strain SiGe channel and preparation method of integrated device

The invention relates to an inverted trapezoidal grid CMOS integrated device with a strain SiGe channel and a preparation method of the integrated device. The manufacture method comprises that an SOI substrate is selected; an N type strain SiGe layer and an N type Si cap layer are grown; an isolated...

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Bibliographische Detailangaben
Hauptverfasser: SONG JIANJUN, XUAN RONGXI, ZHANG HEMING, HU HUIYONG, SHU BIN, LIU XIANGYU, WANG BIN
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The invention relates to an inverted trapezoidal grid CMOS integrated device with a strain SiGe channel and a preparation method of the integrated device. The manufacture method comprises that an SOI substrate is selected; an N type strain SiGe layer and an N type Si cap layer are grown; an isolated channel is formed by an etching technology to separate an NMOS active region from a PMOS active region; P type ions are injected at the surface of the NMOS active region by an ion implantation technology to form a P well; an NMOS grid pattern is formed by photo-etching, a first double-trapezoid groove is formed by an ion beam etching technology, a PMOS grid pattern is formed by photo-etching, and a second double-trapezoid groove is formed by the ion beam etching technology; an oxidation layer is formed to form an NMOS grid medium material and a PMOS grid medium material; the NMOS grid medium material is etched, an NMOS source and drain area is formed by the ion implantation technology, the PMOS grid medium material is etched, and an NMOS source and drain area is formed by the ion implantation technology; the grid medium materials are grown to form NMOS and PMOS grids; and metallization is carried out, the drain, source and grid leads are photo-etched to form the inverted trapezoidal grid CMOS integrated device with the strain SiGe channel.