Silicon carbide VDMOS device and manufacturing method

The invention belongs to the semiconductor technology and particularly relates to a silicon carbide VDMOS device and a manufacturing method. The silicon carbide VDMOS device comprises a silicon carbide N type heavily-doped substrate, a silicon carbide N-epitaxial layer above the silicon carbide N type heavily-doped substrate, Pbase regions arranged at the upper portion of the silicon carbide N-epitaxial layer, a source electrode formed by a silicon carbide P+ contact region in the Pbase regions and an N+ source region, groove poly-silicon in a JFET region denting between the Pbase regions, a silicon dioxide medium denting between the poly-silicon in the JFET region and a semi-conductor, and a P+ region surrounding periphery of the silicon dioxide medium in the JFET region. According to the silicon carbide VDMOS device, a groove gate is arranged, a gate-oxide electric field is optimized, and reliability of the device is improved.