A flip-flop with reduced retention voltage

A flip-flop with reduced retention voltage

The invention provides a flip-flop with reduced retention voltage. A circuit (100) includes a logic gate (133) responsive to a clock signal (103) and to a control signal (104). The circuit also includes a master stage (101) of a flip-flop. The circuit further includes a slave stage (102) of the flip...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SACHIN BAPAT, PRAYAG BHANUBHAI PATEL, MARTIN SAINT-LAURENT, MOHAMED HASSAN ABU-RAHMA, RAMAPRASATH VILANGUDIPITCHAI, ANIMESH DATTA, PEEYUSH KUMAR PARKAR, SEID HADI RASOULI, JAY MADHUKAR SHAH
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:The invention provides a flip-flop with reduced retention voltage. A circuit (100) includes a logic gate (133) responsive to a clock signal (103) and to a control signal (104). The circuit also includes a master stage (101) of a flip-flop. The circuit further includes a slave stage (102) of the flip-flop responsive to the master stage. The circuit further includes an inverter (109) responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage (101) and to the slave stage (102) of the flip-flop. The master stage is responsive to the control signal to control the slave stage.