Wafer-level tin soldering dimpling point and manufacturing method thereof

The invention relates to a wafer-level tin soldering dimpling point and a manufacturing method thereof. The wafer-level tin soldering dimpling point comprises a soldering pad formed on an IC wafer and a passivation layer. The passivation layer is provided with an opening. The surface of the soldering pad is exposed at the opening. The soldering pad is successively provided with a sputtered titanium layer and copper layer. The surface of the sputtered copper layer is provided with an electroplated adhesion layer and barrier layer. The barrier layer is provided with a soldering dimpling point. The soldering dimpling point covers the surface of the barrier layer and side parts of the barrier layer and the adhesion layer. The sizes of the adhesion layer and the barrier layer are smaller than the sizes of the copper layer and the titanium layer. Certain intervals exist between the edges of the adhesion layer and the barrier layer and the edges of the copper layer and the titanium layer. The soldering dimpling point covers the surface of the copper layer at the interval and the side parts of the sputtered titanium layer and copper layer. According to the invention, the contact area of the soldering dimpling point and the sputtered copper layer is increased, the adhesiveness between the soldering dimpling point and the sputtered copper layer is improved, and a layered failure is prevented; in addition, the wafer-level tin soldering dimpling point and the manufacturing method thereof solve the problem of an existing wet method etching technology that an electroplated copper layer is undercut in a sputtered metal layer removing process.