Image processing system based on Field Programmable Gate Array (FPGA)

The invention relates to an image processing system based on a Field Programmable Gate Array (FPGA), and belongs to the field of image processing. The system includes: a video decoding module, an image processing module arranged on the FPGA and a video coding module, wherein the video decoding module includes a LVDS receiving unit, a CCIR-D receiving unit and a SD-SDI receiving unit, and the video coding module includes a DVI coding module and a CCIR-D coding module. According to the invention, the SD-SDI receiving unit adopts an equalizer GS2994, and a clock recovery device GS2965 for strengthening the signal anti-interruption capacity, and adopts a SDRAM sequential to realize conversion of a PAL sequential and a VGA sequential; the chip clock of the SDRAM can meet the requirements of the design at 100 MHZ. The image processing system has small power consumption. The image processing system and the FPGA require no need of occupation of exclusive pins therebetween. The image processing system addresses the problem of complexity of debugging of image processing based on FPGA in the prior art.