Sensing chip packaging structure and preparation method thereof
The invention provides a low-cost and high-reliability packaging and interconnection integration scheme aiming at a sensing chip, and in particular a fingerprint identification chip. According to the scheme, conductive lines, solder plate convex blocks and solder balls are directly manufactured at t...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | The invention provides a low-cost and high-reliability packaging and interconnection integration scheme aiming at a sensing chip, and in particular a fingerprint identification chip. According to the scheme, conductive lines, solder plate convex blocks and solder balls are directly manufactured at the back surface of the protective cover of the sensing chip, and the sensing chip and the solder plate convex blocks on the back surface of the protective cover are directly fit to form electrical connection and the bottom is filled with protection. Then electrical interconnection with a substrate is realized via the conductive lines and the solder balls of the back surface of the protective cover. Finally protection is filled between the protective cover and the substrate so that integral protection of the sensing chip packaging body is realized. According to the structure, the sensing chip is directly led out via the solder plate convex blocks, the conductive lines and the solder balls which are arranged at the back surface of the protective cover so that operation of notching and hole digging on the sensing chip can be avoided and the packaging process is simplified; meanwhile, two times of protection filling is adopted so that product packaging yield rate and reliability can be enhanced; besides, the solder plate convex blocks, the conductive lines and the solder balls arranged on the protective cover can be manufactured by adopting a wafer level technology so that integral packaging cost can be effectively reduced. |
---|