Semiconductor package

Semiconductor package

A stacked semiconductor package in an embodiment includes a first circuit board; a first semiconductor package formed through mounting the first semiconductor element on the first circuit board; a second circuit board; a second semiconductor package formed through mounting a second semiconductor ele...

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Hauptverfasser: MIYAKOSHI, TAKESHI, HOSOYAMADA, SUMIKAZU, KUMAGAYA, YOSHIKAZU, CHIKAI, TOMOSHIGE, SAKUMOTO, SHOTARO, NAKAMURA, SHINGO, MATSUBARA, HIROAKI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator MIYAKOSHI, TAKESHI
HOSOYAMADA, SUMIKAZU
KUMAGAYA, YOSHIKAZU
CHIKAI, TOMOSHIGE
SAKUMOTO, SHOTARO
NAKAMURA, SHINGO
MATSUBARA, HIROAKI
description A stacked semiconductor package in an embodiment includes a first circuit board; a first semiconductor package formed through mounting the first semiconductor element on the first circuit board; a second circuit board; a second semiconductor package formed through mounting a second semiconductor element on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_CN104966702A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>CN104966702A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_CN104966702A3</originalsourceid><addsrcrecordid>eNrjZBANTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBVqXmpJfHOfoYGJpZmZuYGRo7GxKgBAIbeIU0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package</title><source>esp@cenet</source><creator>MIYAKOSHI, TAKESHI ; HOSOYAMADA, SUMIKAZU ; KUMAGAYA, YOSHIKAZU ; CHIKAI, TOMOSHIGE ; SAKUMOTO, SHOTARO ; NAKAMURA, SHINGO ; MATSUBARA, HIROAKI</creator><creatorcontrib>MIYAKOSHI, TAKESHI ; HOSOYAMADA, SUMIKAZU ; KUMAGAYA, YOSHIKAZU ; CHIKAI, TOMOSHIGE ; SAKUMOTO, SHOTARO ; NAKAMURA, SHINGO ; MATSUBARA, HIROAKI</creatorcontrib><description>A stacked semiconductor package in an embodiment includes a first circuit board; a first semiconductor package formed through mounting the first semiconductor element on the first circuit board; a second circuit board; a second semiconductor package formed through mounting a second semiconductor element on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151007&amp;DB=EPODOC&amp;CC=CN&amp;NR=104966702A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151007&amp;DB=EPODOC&amp;CC=CN&amp;NR=104966702A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MIYAKOSHI, TAKESHI</creatorcontrib><creatorcontrib>HOSOYAMADA, SUMIKAZU</creatorcontrib><creatorcontrib>KUMAGAYA, YOSHIKAZU</creatorcontrib><creatorcontrib>CHIKAI, TOMOSHIGE</creatorcontrib><creatorcontrib>SAKUMOTO, SHOTARO</creatorcontrib><creatorcontrib>NAKAMURA, SHINGO</creatorcontrib><creatorcontrib>MATSUBARA, HIROAKI</creatorcontrib><title>Semiconductor package</title><description>A stacked semiconductor package in an embodiment includes a first circuit board; a first semiconductor package formed through mounting the first semiconductor element on the first circuit board; a second circuit board; a second semiconductor package formed through mounting a second semiconductor element on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBANTs3NTM7PSylNLskvUihITM5OTE_lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBVqXmpJfHOfoYGJpZmZuYGRo7GxKgBAIbeIU0</recordid><startdate>20151007</startdate><enddate>20151007</enddate><creator>MIYAKOSHI, TAKESHI</creator><creator>HOSOYAMADA, SUMIKAZU</creator><creator>KUMAGAYA, YOSHIKAZU</creator><creator>CHIKAI, TOMOSHIGE</creator><creator>SAKUMOTO, SHOTARO</creator><creator>NAKAMURA, SHINGO</creator><creator>MATSUBARA, HIROAKI</creator><scope>EVB</scope></search><sort><creationdate>20151007</creationdate><title>Semiconductor package</title><author>MIYAKOSHI, TAKESHI ; HOSOYAMADA, SUMIKAZU ; KUMAGAYA, YOSHIKAZU ; CHIKAI, TOMOSHIGE ; SAKUMOTO, SHOTARO ; NAKAMURA, SHINGO ; MATSUBARA, HIROAKI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_CN104966702A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MIYAKOSHI, TAKESHI</creatorcontrib><creatorcontrib>HOSOYAMADA, SUMIKAZU</creatorcontrib><creatorcontrib>KUMAGAYA, YOSHIKAZU</creatorcontrib><creatorcontrib>CHIKAI, TOMOSHIGE</creatorcontrib><creatorcontrib>SAKUMOTO, SHOTARO</creatorcontrib><creatorcontrib>NAKAMURA, SHINGO</creatorcontrib><creatorcontrib>MATSUBARA, HIROAKI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MIYAKOSHI, TAKESHI</au><au>HOSOYAMADA, SUMIKAZU</au><au>KUMAGAYA, YOSHIKAZU</au><au>CHIKAI, TOMOSHIGE</au><au>SAKUMOTO, SHOTARO</au><au>NAKAMURA, SHINGO</au><au>MATSUBARA, HIROAKI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package</title><date>2015-10-07</date><risdate>2015</risdate><abstract>A stacked semiconductor package in an embodiment includes a first circuit board; a first semiconductor package formed through mounting the first semiconductor element on the first circuit board; a second circuit board; a second semiconductor package formed through mounting a second semiconductor element on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor package
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T15%3A18%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MIYAKOSHI,%20TAKESHI&rft.date=2015-10-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ECN104966702A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true