Semiconductor memory

A synchronous dynamic random access memory is capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock CLK and includes a plurality of memory banks 12, 14 each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit (70, 108) for receiving a row address strobe signal RAS¯ and latching a logic level of the row address strobe signal RAS¯ in response to the clock CLK, an address input circuit for receiving an externally generated address SRA10, SRA11 selecting one of the memory banks, and a circuit (540, 542) for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank 12, 14 selected by the address, and inactivation signals to unselected memory banks 12, 14 when the latched logic level is a first logic level, so that the selected memory bank 12, 14 responsive to the activation signal operates in the active cycle while the unselected memory banks (12, 14) responsive to the inactivation signals operate in the precharge cycle.