Device and method for floating point complex number parallel addition and subtraction

The invention discloses a device and method for floating point complex number parallel addition and subtraction. The device comprises a plurality of source vector registers, a data selector, an arithmetic unit and a target vector register, wherein each source vector register is used for storing a plurality of floating point complex numbers; each floating point complex number comprises a floating point number serving as a real part and a floating point number serving as a virtual part; the data selector is used for reading the real part floating point numbers and the virtual part floating point numbers of the floating point complex numbers in each source vector register, and pairwise transmitting the real part floating point numbers and the virtual part floating point numbers in each source vector register to the arithmetic unit respectively; the arithmetic unit is used for performing operation on data read by the data selector according to an operation type and a data type; and the target vector register is used for storing the operation result of the arithmetic unit. According to the device, parallel addition and subtraction operation of the floating point complex numbers is realized through different data provided for the arithmetic unit by the data selector, so that hardware resources are saved.