Structure and method of manufacturing 3D integration scheme

Structure and method of manufacturing 3D integration scheme

The disclosure relates to a structure and method of manufacturing a 3D integration scheme. The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semicon...

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Bibliographische Detailangaben
Hauptverfasser: DOUGLAS C. LA TULIPE JR, JOHN W. GOLZ, SPYRIDON SKORDAS, POOJA R. BATRA, SUBRAMANIAN S. IYER, KEVIN R. WINSTEL
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:The disclosure relates to a structure and method of manufacturing a 3D integration scheme. The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.