Testing method and testing structure

The invention provides a testing method and a testing structure and relates to the technical field of semiconductors. The testing method comprises the steps of forming the testing structure including at least two capacitors equal in design value and comparing actual values of at least two capacitors to accurately judge whether a graphical process produces offset or not. By means of the testing method, the overlapping and interval problems can be monitored and controlled. The testing method is simple and effective. The testing structure can be applied to the testing method and used for testing whether the graphical process produces offset or not.