Strip level substrate including warpage preventing member and method of manufacturing the same

Disclosed herein is a strip level substrate having a plurality of unit level substrate regions partitioned by unit saw lines, including: a plurality of wiring layers and a plurality of insulating layers that are alternately stacked; and warpage preventing members disposed in unit saw line regions of...

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Bibliographische Detailangaben
Hauptverfasser:	PARK, JONG TAE, EUN, SANG IL, KANG, HO SHIK
Format:	Patent
Sprache:	eng
Schlagworte:	CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Beschreibung
Zusammenfassung:	Disclosed herein is a strip level substrate having a plurality of unit level substrate regions partitioned by unit saw lines, including: a plurality of wiring layers and a plurality of insulating layers that are alternately stacked; and warpage preventing members disposed in unit saw line regions of an insulating layer bonded to a carrier member among the plurality of insulating layers, in order to improve warpage characteristics of the strip level substrate.