Transmission pulse upper and lower edge control system

The invention relates to a transmission pulse upper and lower edge control system, which solves the problems that an FIR (finite impulse response) filter of the existing system needs to use multiplying unit and adder resources in an FPGA (field programmable gate array), and can not meet the requirements of small time delay and low power consumption of a secondary radar. Input baseband signals are ASK signals and are output to the input of an FPGA chip, the output of the FPGA chip is connected with a D/A (digital-to-analog) converter, a clock is connected with the FPGA chip and the D/A converter, the output of the D/A converter is connected with an intermediate frequency amplifier, the output of the intermediate frequency amplifier is connected with a frequency mixer, the frequency mixer is connected with a local oscillator, the output of the frequency mixer is connected with the input of the radio frequency power amplifier, the clock of the FPGA chip is 400MHz, the output intermediate frequency digital signal carrier frequency is 80MHz, the modulation mode is ASK modulation, output intermediate frequency digital signals complete pulse upper and lower edge control, the sampling frequency of the D/A converter is 400MHz, intermediate frequency signals and the local oscillator are subjected to up-conversion by the frequency mixer to obtain radio frequency signals required to be transmitted, and then, power amplification output is carried out.