Chip testing method
The invention discloses a chip testing method which is characterized by simultaneously testing different varieties or types of chips on the same silicon wafer by using DFM (Data Failure Memory) resource of an SOC (System on Chip) tester. The chip testing method comprises the following steps of carry...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | The invention discloses a chip testing method which is characterized by simultaneously testing different varieties or types of chips on the same silicon wafer by using DFM (Data Failure Memory) resource of an SOC (System on Chip) tester. The chip testing method comprises the following steps of carrying out whole-process conventional test on different types of chips and recording BIN information; storing the recorded BIN information by using a DFM module of the SOC tester; processing the BIN information by using a tester CPU (Central Processing Unit), separating test results of different products and accurately uploading the test results to corresponding servers, thereby implementing mass production test of a plurality of chips. |
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