Low-capacitance transient voltage restraint device and manufacturing method thereof

The invention relates to a low-capacitance transient voltage restraint device and a manufacturing method thereof. The device comprises a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a buried layer area formed between the semiconductor substrate and the epitaxial layer, and an isolation area which is formed in the epitaxial layer and extends to the substrate. The device further comprises a TVS tube, at least one first diode and at least one second diode, wherein the TVS tube comprises a base area formed in the isolation area and an emitting area formed in the base area, each first diode comprises a diffusion area formed in the epitaxial layer in the buried layer area, a transmitting area formed in the diffusion area, and a base area formed in the epitaxial area in the buried layer area, each second diode comprises a base area formed in the isolation area, a transmitting area formed in the epitaxial area, a first electrode formed on the other side of the semiconductor substrate, and a metal wiring layer formed on the surface of the epitaxial layer and used for forming the transient voltage restraint device.