Reconfigurable circuit as well as decoder

The invention relates a digital decoder which is used in a reconfigurable circuit and is used for decoding digital pulse. The digital decoder comprises a phase indicator module which has an input which is coupled to a reference pulse input and a data pulse input. The phase indicator module has a timing information output which provides logic values which indicate ascending and descending edges of a pulse appearing on the reference pulse input and the data pulse input. A phase decoder module has an input which is coupled to the timing information input and outputs a decoded binary data value. In the operation, the phase decoder module is used for comparing at least two of the logic values at the timing information output with signals of front and rear edges of one of the pulses of the phase input so as to determine that the pulse of the phase input reaches a sequential sequence and further provides the decoded binary data value.