Time sequence determining method and device of integrated circuit chip

The invention provides a time sequence determining method and device of an integrated circuit chip. The time sequence determining method includes subjecting a top module and at least two submodules of an integrated circuit chip to be designed to synthesization, overall arrangement and clock network design generation; extracting a boundary time sequence model according to the clock network of the submodules and the top module; if the boundary time sequence model meets the first time sequence conditions, designing wiring of the submodules and the top module; extracting an electric parameter model according to the wired submodules and the top module; if the electric parameter model meets the second time sequence condition, splicing the submodules and the top module and extracting a transistor model; if the transistor model meets the third time sequence condition, determining the time sequence of the integrated circuit chip. By the time sequence determining method and device, different time sequence models are extracted for different stages of integrated circuit chip design, and balance between speed and accuracy of the time sequence analysis is realized.