Device and method for carrying out complex multiplication and butterfly calculation by virtue of floating point unit of processor

The invention provides a device and a method for carrying out complex multiplication and butterfly calculation by virtue of a floating point unit of a processor. The floating point unit is divided into a floating point addition unit and a floating point multiplication unit, wherein a few interconnection lines are additionally arranged between data ports of the floating point addition unit and the floating point multiplication unit; a special data path is formed between the floating point addition unit and the floating point multiplication unit; real and imaginary components of a complex are input into a data port of the floating point unit according to a determined ordering rule; the floating point complex multiplication and floating point complex butterfly calculation can be achieved under the control of decoding signals generated by a decoding unit. According to the method and the device, hardware resources are saved; compared with the existing complex multiplication and butterfly calculation function unit, the flexibility is further improved; meanwhile, parallel and flow calculation of a large amount of data can be well implemented; high real-time performance and high resource utilization rate are obtained.